The present invention relates to a simulator and a simulation method for simulating, on a host computer, a target program prepared for execution on a target computer.
In general, a simulator has as data an instruction sequence of a target program which is prepared for execution on a target computer, and performs interpretation and execution of those data per instruction through a host computer on which the simulator operates, so as to simulate an operation of the target computer. Specifically, since an execution environment including a central processing unit (CPU) and a memory differs between the target computer and the host computer, the simulator establishes on the host computer a storage area (target memory) and a CPU register area (target register) simulating the execution environment of the target computer, interprets the instructions of a target CPU through the software and performs processes corresponding to those instructions relative to the target memory so as to simulatively realize the operation of the target computer.
Another simulator is known which has a table of the number of clocks required for executing each instruction on the target computer and adds a value thereof per instruction to roughly estimate the total number of execution clocks. In such a simulator, by adding a peripheral circuit simulator which operates synchronously with the obtained number of clocks, an interrupt can be simulated which is synchronous with the number of execution clocks from a timer, an external communication device or the like.
However, in the foregoing simulation methods, since it takes time to interpret each instruction through the software, the execution speed is much lower as compared with an operation of the intrinsic target computer. In view of this, a simulation method which is capable of solving such a problem, that is, capable of a high-speed simulation, has been proposed.
For example, Japanese First (unexamined) Patent Publication No. 6-250874 discloses one example of a high-speed simulator. In the manner which will later be discussed in conjunction with the drawing, the example interprets the instructions of the target program and converts them into the corresponding simulation function calling means in advance. Therefore, it is not required to carry out the interpretation of the instructions through the software upon execution of the simulation so that the simulation can be performed at high speed.
In the foregoing conventional simulator, however, since the target CPU and the host CPU differ from each other, the number of execution clocks required for execution of the target program at the target CPU can not be derived from the number of execution clocks required for execution of the converted program at the host CPU. That is, data about the number of execution clocks required for actually running the target program on the target computer including the target CPU can not be obtained.
Further, in the conventional simulator, since the data about the number of execution clocks can not be obtained, an interrupt from a peripheral circuit, such as a timer, synchronous with the CPU clock can not be simulated.
An influence of the foregoing problems is significant when a built-in type CPU is a target of the simulation since the process flow frequently changes upon interrupts from peripheral circuits in a program for the built-in type CPU.